1. Field of the Invention
The present invention relates to a layer-stacked wiring, a method of manufacturing the layer-stacked wiring, a semiconductor using the layer-stacked wiring, and a method of manufacturing the semiconductor using the layer-stacked wiring and more particularly to the layer-stacked wiring, which employs a microcrystalline silicon thin film, to be applied to a gate electrode of a TFT (Thin Film Transistor) or a like, and the method of manufacturing the layer-stacked wiring and to the semiconductor device using the layer-stacked wiring and the method for manufacturing the semiconductor device.
The present application claims priority of Japanese Patent Application No. 2006-070653 filed on Mar. 22, 2006, which is hereby incorporated by reference.
2. Description of the Related Art
For example, in a conventional LCD (Liquid Crystal Display) device known as a representative display device, use of an amorphous silicon thin film which employs an amorphous silicon thin film as its active layer is in the mainstream. However, low mobility of the amorphous silicon thin film causes the LCD device to be unable to be high-definition and, therefore, attention is focused on a polycrystalline silicon TFT which uses a polycrystalline silicon thin film having high mobility as its active layer.
On the other hand, due to diversification of use of the LCD devices, there is a strong need for making the LCD device thin and small in size and, responsive to these needs, efforts have been made so that a driving circuit made up of a TFT is formed on an active-matrix substrate. However, the formation of the TFT to be employed as the TFT for a driving circuit using an amorphous silicon thin film is not desirable in terms of an operation rate and driving capability and it is, therefore, necessary that the TFT for a driving circuit is formed by using a polycrystalline thin film having higher mobility. As a method for forming a polycrystalline thin film, from a view point of a lowered process temperature, improvement of a throughput, and low costs, the use of a laser annealing method in which a polycrystalline thin film can be formed on a low-priced low-temperature glass substrate now becomes mainstream.
However, the polycrystalline TFT has a problem in that it is less reliable when used as a gate electrode and in that it is not easy to obtain a gate electrode of low resistance, thus causing it difficult to realize the LCD with high-definition using the polycrystalline TFT. To solve this problem, polycrystalline silicon TFTs are disclosed in, for example, Patent References 1 (Japanese Patent No. 3282528), 2 (Japanese Patent No. 3613221), 3 (Japanese Patent Application Laid-open No. 2004-336073), and 4 (Japanese Patent Application Laid-open No. 2004-281506) in which a gate electrode is constructed by using a layer-stacked wiring made up of a microcrystalline silicon thin film (lower layer) and a metal thin film (upper layer).
FIG. 11 is a cross-sectional view showing a conventional polycrystalline silicon TFT in which the layer-stacked wiring using the above microcrystalline thin film disclosed in, for example, the above Patent Reference 1 is employed as its gate electrode. The polycrystalline silicon TFT 100, as shown in FIG. 11, includes an insulating substrate 101, a front-end insulating film 102 formed on the insulating substrate 101, a polycrystalline silicon thin film 103 formed on the front-end insulating film 102, a source region 104 formed on one end of the polycrystalline silicon thin film 103 and a drain region 105 formed on the other end of the polycrystalline silicon thin film 103, a gate insulating film 106 formed on the polycrystalline silicon thin film 103, a gate electrode having a microcrystalline silicon thin film (lower layer) 107 formed on the gate insulating film 106 and a metal thin film (upper layer) 108 formed on the microcrystalline silicon thin film 107. Moreover, the polycrystalline silicon TFT 100 also includes an interlayer insulating film 110 formed on all entire surfaces of the gate insulating film 106 including the surface of the gate electrode 109, a source electrode 113 being in contact with the source region 104 via a contact hole 111 obtained by forming a hole through the interlayer insulating film 110, and a drain electrode 114 being in contact with the drain region 105 via a contact hole 112 obtained by forming a hole through the interlayer insulating film 110.
Here, the microcrystalline silicon thin film 107 making up the gate electrode 109 is a silicon thin film deposited by a plasma CVD (Chemical Vapor Deposition), in a crystal structure of which extremely fine crystal grains and amorphous grains exist in a mixed manner. The deposition temperature of the microcrystalline silicon thin film is about 300° C. which is considerably lower when compared with the temperature of 600° C. applied in a low-pressure CVD method or an atmospheric pressure CVD method generally used as a deposition method of the conventional polycrystalline thin film and, the therefore, this method is excellent in terms of a throughput of a deposition process and manufacturing costs, providing an advantage of being a highly productive method. The microcrystalline silicon thin film 107 also serves to prevent an excess release of hydrogen from the gate electrode 109 and the polycrystalline silicon thin film making up an active later.
Moreover, the resistance of the microcrystalline thin film, due to its existence of the fine crystal grains, can be made lower to the same degree as in the polycrystalline silicon thin film. Therefore, by applying the layer-stacked wiring formed by stacking a metal thin film on the microcrystalline silicon thin film, reliability of the gate electrode is improved and low-resistance of the gate electrode is realized, which makes it easy to achieve an LCD device with high definition.
However, the conventional layer-stacked wiring made up of the microcrystalline silicon thin film and metal thin film has a problem in that the occurrence of a silicide formation reaction between the microcrystalline silicon thin film serving as the lower layer and the metal thin film serving as the upper layer causes peeling of the microcrystalline silicon thin film. That is, when the layer-stacked wiring as described above is to be applied to a gate electrode of the polycrystalline silicon TFT, in the process of manufacturing the polycrystalline silicon TFT, an annealing process (activating process) to activate an impurity such as phosphorus, boron, or a like implanted in advance into the polycrystalline thin film and a hydrogenating process to terminate an orbit being in an unbonded state (dangling bond) existing in the polycrystalline thin film and at an interface between the polycrystalline thin film and gate insulating film by using hydrogen are required. In each of the annealing process and hydrogenating process, heat treatment to be performed at a temperature being higher than at a deposition temperature for the microcrystalline silicon thin film and metal thin film is necessary and, as a result, the occurrence of the above-described silicide formation reaction affected by the high-temperature heat treatment is unavoidable between the microcrystalline silicon thin film and metal thin film, both being already formed.
If the silicide formation reaction occurs excessively between the microcrystalline silicon thin film serving as the lower layer and the metal thin film serving as the upper layer, a crystal making up a crystal structure of the microcrystalline silicon thin film is changed from its powder-like shape to its cylinder-like shape. During this change in its crystalline shape, a change in volume of the microcrystalline silicon thin film occurs, which causes the occurrence of voids in the microcrystalline silicon thin film or at an interface between the microcrystal thin film serving as the lower layer and metal thin film serving as the upper layer, which further causes the occurrence of peeling of the microcrystalline silicon thin film affected by the voids at a final stage.
Thus, the formation of the microcrystalline silicon thin film by employing the plasma CVD method provides an advantage of being the more highly productive when compared with the formation of the polycrystalline thin film by using the low-pressure CVD method or atmospheric pressure CVD method. On the other hand, in order to respond to a need for further improvement of productivity, the formation of the microcrystalline silicon thin film under a condition of a higher deposition rate using the plasma CVD method is required. However, in general, there is a tendency that quality of a thin film formed under a condition of a higher deposition rate degrades easily. Therefore, the degradation of the quality of the microcrystalline silicon thin film causes the acceleration of the silicide formation reaction between the microcrystalline silicon thin film and metal thin film to be formed on the microcrystalline silicon thin film serving as its upper layer, which leads to easy peeling of the microcrystalline silicon thin film and, as a result, further to peeling of the layer-stacked wiring.